1. Field
Exemplary embodiments of the present invention relate generally to a semiconductor design technology, and more particularly, to a refresh control circuit for a semiconductor memory device that is capable of performing a target refresh operation.
2. Description of the Related Art
A memory device may typically include a plurality of memory cells for storing data in the form of stored charges. Each memory cell may typically include a capacitor that stores charges (i.e., data) and a transistor that serves as a switch controlling the flow of charges to and from the capacitor. Whether a data is in a ‘high’ logic level (i.e., a logic value ‘1’) or a ‘low’ logic level (i.e., a logic value ‘0’) is decided based on whether there are charges in the capacitor of a memory cell including the data, that is, whether the terminal voltage of the capacitor is high or low.
Data are retained in the form of charges that are accumulated in a capacitor. Therefore, theoretically, there should be no power consumption in simply retaining the data. However, because of a current leak due to a PN junction of a transistor, the initial amount of charges that are stored in a capacitor may gradually disappear, thereby causing data loss. To prevent this data loss, the data of a memory cell has to be read before the data is lost, and then the memory cell has to be re-charged to refresh the charges based on the read data. This operation has to be performed periodically to retain the data and is known in the art as a refresh operation.
The refresh operation is carried out whenever a refresh command is inputted from a memory controller to a memory. The memory controller may repeatedly input the refresh command to the memory at a predetermined time interval which is determined in consideration of a data retention time of the memory device. The data retention time of the memory device may represent how long a memory cell may retain its data without performing a refresh operation. Since the memory cells are designed to have a data retention time which is not shorter than a predetermined standard, the term between the refresh operations may be decided based on the predetermined standard.
However, when the amount of charges stored in a memory cell is affected by the active-precharge of a word line that is disposed adjacent to a word line coupled to the memory cell, the data of the memory cell may be deteriorated within a shorter time than the refresh term. This phenomenon is called a Row Hammering effect.
FIG. 1 is a schematic diagram illustrating a portion of a cell array that is included in a memory device. In the drawing, ‘BL0’ and ‘BL1’ represent bit lines.
Referring to FIG. 1, ‘WLK−1’, ‘WLK’ and ‘WLK+1’ are three word lines that are disposedside by side in the inside of a cell array. The word line WLK marked with ‘ATTACK_WL’ may be a word line that is activated many times, a word line whose frequency of being activated is high, or a word line that is activated for a long time. The word line WLK−1 and the word line WLK+1 are word lines that are disposed adjacent to the word line WLK. Also, ‘CELL_K−1’, ‘CELL_K’, ‘CELL_K’ are memory cells that are coupled to the word line WLK−1, the word line WLK, and the word line WLK+1, respectively. The memory cells CELL_K−1, CELL_K, and CELL_K+1 may include cell transistors TR_K−1, TR_K and TR_K+1 and cell capacitors CAP_K−1, CAP_K and CAP_K+1, respectively.
In FIG. 1, when the word line WLK is activated many times, frequently activated, or activated for a long time, the voltage of the word line WLK may toggle frequently or the voltage of the word line WLK may be kept high for a long time. This may affect the data that are stored in the memory cells CELL_K−1 and CELL_K which are coupled to the word lines WLK−1 and WLK+1, respectively, due to a coupling effect occurring between the word line WLK and the word line WLK−1 and between the word line WLK and the word line WLK+1. The Row Hammering effect may shorten the time that the memory cells retain the data stored therein. The Row Hammering effect may be a serious concern, especially for high density semiconductor memory devices due to the increased proximity of neighboring word lines.
Normal refresh operations which sequentially refresh the plurality of word lines in a memory device when a refresh command is inputted do not specifically address data loss of memory cells due to the Row Hammering effect. Hence a new refresh operation is needed.